Semiconductor device and method for making the same

ABSTRACT

A semiconductor device comprises a substrate, at least one electronic component mounted on the substrate, an encapsulant formed on the substrate and at least partially encapsulating the at least one electronic component, a shielding layer formed on the encapsulant, a thermal interface layer formed on the shielding layer, and a metal lid formed on the thermal interface layer.

TECHNICAL FIELD

The present application generally relates to semiconductor devices, andmore particularly, to a semiconductor device and a method for making thesame.

BACKGROUND OF THE INVENTION

The semiconductor industry is constantly faced with complex integrationchallenges as consumers want their electronic devices to be smaller,faster and have higher performances. In cutting edge 5G devices such asportable multimedia devices, it is common to integrate both a processingsystem and antenna(s) into one package. In such configuration, multipleelectronic components may be integrated in a smaller package, meetingthe consumers' needs to encompass more functional modules in a smallerdevice. However, such high-level integration requires higher interfacepin-counts and less thickness, and thus generates more heat and has aless effective heat dissipation. In such cases, the heat accumulatedwithin the package may cause package warpage issue and harm the functionof the system.

Therefore, a need exists for a semiconductor package with improved heatmanagement.

SUMMARY OF THE INVENTION

An objective of the present application is to provide an apparatus forheat management of a semiconductor device.

According to an aspect of embodiments of the present application, asemiconductor device is provided. The semiconductor device comprises: asubstrate; at least one electronic component mounted on the substrate;an encapsulant formed on the substrate and at least partiallyencapsulating the at least one electronic component; a shielding layerformed on the encapsulant; a thermal interface layer formed on theshielding layer; and a metal lid formed on the thermal interface layer.

According to an aspect of embodiments of the present application, asemiconductor device is provided. The semiconductor device comprises: asubstrate; at least one electronic component mounted on the substrate;an encapsulant formed on the substrate and at least partiallyencapsulating the at least one electronic component; a thermal interfacelayer formed on the encapsulant; a metal lid formed on the thermalinterface layer; and a shielding layer formed on the substrate andcovering the metal lid, the thermal interface layer and the encapsulant.

According to another aspect of embodiments of the present application,methods for making the semiconductor devices according to the aboveaspects are provided.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory only,and are not restrictive of the invention. Further, the accompanyingdrawings, which are incorporated in and constitute a part of thisspecification, illustrate embodiments of the invention and together withthe description, serve to explain principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings referenced herein form a part of the specification.Features shown in the drawing illustrate only some embodiments of theapplication, and not of all embodiments of the application, unless thedetailed description explicitly indicates otherwise, and readers of thespecification should not make implications to the contrary.

FIG. 1A is a cross-sectional view illustrating a semiconductor deviceaccording to an embodiment of the present application.

FIGS. 1B and 1C are enlarged views illustrating a portion of thesemiconductor device of FIG. 1A according to some embodiments of thepresent application.

FIG. 1D is a cross-sectional view illustrating a semiconductor devicewith discrete antenna packages according to an embodiment of the presentapplication.

FIG. 2A is a cross-sectional view illustrating a semiconductor devicewith top surfaces of two electronic components being exposed to ashielding layer according to another embodiment of the presentapplication.

FIGS. 2B and 2C are enlarged views illustrating a portion of thesemiconductor device of FIG. 2A according to some embodiments of thepresent application.

FIGS. 3A, 3B and 4 are cross-sectional views illustrating asemiconductor device with encapsulated semiconductor package mounted ona substrate according to some embodiments of the present application.

FIG. 5A is a cross-sectional view illustrating a semiconductor deviceaccording to another embodiment of the present application.

FIGS. 5B and 5C are enlarged views illustrating a portion of thesemiconductor device of FIG. 5A according to some embodiments of thepresent application.

FIG. 6A is a cross-sectional view illustrating a semiconductor deviceaccording to another embodiment of the present application.

FIGS. 6B and 6C are enlarged views illustrating a portion of thesemiconductor device of FIG. 6A according to some embodiments of thepresent application.

FIGS. 7 and 8 are cross-sectional views illustrating a semiconductordevice with encapsulated semiconductor package mounted on a substrateaccording to some embodiments of the present application.

FIG. 9A is a flowchart illustrating a method 900 for making asemiconductor device according to an embodiment of the presentapplication.

FIGS. 9B-9F are cross-sectional views illustrating various steps of themethod for making a semiconductor device shown in FIG. 9A.

FIG. 10A is a flowchart illustrating a method 1000 for making asemiconductor device according to another embodiment of the presentapplication.

FIGS. 10B-10F are cross-sectional views illustrating various steps ofthe method for making a semiconductor device shown in FIG. 10A.

The same reference numbers will be used throughout the drawings to referto the same or like parts.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following detailed description of exemplary embodiments of theapplication refers to the accompanying drawings that form a part of thedescription. The drawings illustrate specific exemplary embodiments inwhich the application may be practiced. The detailed description,including the drawings, describes these embodiments in sufficient detailto enable those skilled in the art to practice the application. Thoseskilled in the art may further utilize other embodiments of theapplication, and make logical, mechanical, and other changes withoutdeparting from the spirit or scope of the application. Readers of thefollowing detailed description should, therefore, not interpret thedescription in a limiting sense, and only the appended claims define thescope of the embodiment of the application.

In this application, the use of the singular includes the plural unlessspecifically stated otherwise. In this application, the use of “or”means “and/or” unless stated otherwise. Furthermore, the use of the term“including” as well as other forms such as “includes” and “included” isnot limiting. In addition, terms such as “element” or “component”encompass both elements and components including one unit, and elementsand components that include more than one subunit, unless specificallystated otherwise. Additionally, the section headings used herein are fororganizational purposes only, and are not to be construed as limitingthe subject matter described.

As used herein, spatially relative terms, such as “beneath”, “below”,“above”, “over”, “on”, “upper”, “lower”, “left”, “right”, “vertical”,“horizontal”, “side” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The device may be otherwise oriented (rotated 90 degrees orat other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. It should be understoodthat when an element is referred to as being “connected to” or “coupledto” another element, it may be directly connected to or coupled to theother element, or intervening elements may be present.

FIG. 1A shows a semiconductor device 100 with multiple electroniccomponents mounted on a substrate 110 of the semiconductor device 100,according to an embodiment of the present application. As shown in FIG.1A, some of the electronic components are encapsulated, and furthercovered by a shielding layer, a thermal interface layer and a metal lidwhich together provide heat management for the semiconductor device 100,especially the electronic components encapsulated therein.

Specifically, a plurality of electronic components 120, 130, 140 and 150are mounted on both sides of the substrate 110, and the electroniccomponents are electrically connected to the conductive structures (notshown) within the substrate 110. In one embodiment, the substrate 110includes one or more embedded antenna members (not shown). Theelectronic components mounted on the substrate 110 may be semiconductordice 120, discrete devices 130 and 140, and dielectric members 150. Thedielectric members 150 may improve transmission and reception ofcorresponding embedded antenna members, respectively. In someembodiments, the discrete device 140 is a board-to-board connector,which may be electrically connected to an electronic component or thesubstrate 110 of the semiconductor device 100, and may be configured toelectrically connect to other devices. Preferably, the board-to-boardconnector electrically connects the embedded antenna members to otherdevices. Some of the electronic components such as the semiconductordice 120 and the discrete device 130 may require encapsulation and EMIshielding, while some other electronic components such as the discretedevices 140 and the dielectric members 150 may not require the sameprotections. The present application achieves an improved heatmanagement by further stacking a multi-layer structure with theencapsulation and the shielding layer, which is further elaboratedbelow.

Further referring to the semiconductor device 100 shown in FIG. 1A, in apreferred embodiment, the semiconductor dice 120, the discrete devices130, 140 may be mounted on one side of the substrate 110, and thedielectric members 150 may be mounted on the other side of the substrate110. As aforementioned, due to different practical needs in productionand usage, the semiconductor dice 120 and discrete device 130, and thediscrete devices 140 and dielectric members 150 may not require the sameencapsulation and EMI shielding. An encapsulant 160 is thereforedisposed on a part of the electronic components mounted on the substrate110, i.e., the encapsulant 160 covers the semiconductor dice 120 and thediscrete device 130. In contrast, the other electronic components, i.e.,the discrete devices 140 and the dielectric members 150, remain notencapsulated and not shielded. The encapsulant 160 covering the part ofthe electronic components may form an encapsulant cuboid on thesubstrate 110. A shielding layer 170 is formed to cover at least part ofthe outer surface of the encapsulant cuboid. Preferably, the shieldinglayer 170 covers all the outer surface of the encapsulant cuboid. Assuch, the shielding layer 170 includes a top section covering a topsurface of the encapsulant cuboid, and a lateral section coveringlateral surfaces of the encapsulant cuboid, thereby the shielding layer170 has a shape that conforms to the shape of the encapsulant 160.

A thermal interface layer 180 is further formed on the shielding layer170. Preferably, the thermal interface layer 180 may fully cover the topsection of the shielding layer 170, but may not cover the lateralsection of the shielding layer 170. That is, the thermal interface layer180 conforms to the top section of the shielding layer 170. A metal lid190 is further disposed on the thermal interface layer 180. Preferably,the metal lid 190 may fully cover a top surface of the thermal interfacelayer 180. That is, the metal lid 190 conforms to the top surface of thethermal interface layer 180.

As illustrated above, in the semiconductor device 100 shown in FIG. 1A,the electronic components 120 and 130 are covered by a stack-upstructure of the encapsulant 160, the shielding layer 170, the thermalinterface layer 180 and the metal lid 190 in bottom-to-top order. Ofnote, heights of layers of the stack-up structure depicted in FIG. 1Aare only illustrative, not representing the actual proportion of heightsof layers in the stack-up structure. The shielding layer 170 may beformed by depositing a shielding material such as metals, conductingplastics and conducting polymers. The thermal interface layer 180 may beformed on the shielding layer 170 by dispensing a thermal interfacematerial onto the shielding layer 170. The thermal interface layer 180is used for enhancing thermal coupling between a heat-producing deviceand a heat dissipating device. Specifically speaking, at each contactinterface, a thermal boundary resistance exists to impede heatdissipation, and electronic performance and device lifetime can degradedramatically under continuous overheating and large thermal stress atthe contact interfaces. The thermal interface layer 180 may reduce thethermal boundary resistance between layers, enhance thermal managementperformance, as well as tackle application requirements such as lowthermal stress between materials of different thermal expansioncoefficients, low elastic modulus or viscosity, flexibility, andreusability. The thermal interface layer 180 transfers heat away fromthe electronic components under the thermal interface layer 180 throughthe encapsulant 160 and the shielding layer 170 to the heat-spreadingmetal lid 190. In some embodiments, the thermal interface material canbe thermally conductive, dispensable materials, preferably thermalgreases, thermal adhesives, thermal gap fillers, liquid metal, andsolder paste. In an embodiment, the thermal interface material is anepoxy compound, which may be used for easy bonding to metals, ceramics,most plastics and a wide variety of other materials. In anotherembodiment, the thermal interface material includes solder paste whichhas improved thermal conductivity over typical thermal interfacematerial. Preferably, the solder paste is Ag—In solder alloy.Specifically, the thermal interface material may be a solder preform,that is, a solid, flat, manufactured-shape of solder, and a flux may beapplied to coat the solder preform. The metal lid 190 is usually made ofhigh thermal conductive metallic materials for efficient heatdissipation from devices in a semiconductor package. In the presentapplication, the metal lid 190 may function in combination with thethermal interface layer 180 to provide better heat dissipation forelectronic components inside the corresponding encapsulant. The metallid 190 is preferably made of copper, aluminum, and copper-tungstenalloy. It can be appreciated that other suitable materials can be usedto form the metal lid 190. With the thermal interface layer 180 and themetal lid 190 conducting heat away from the electronic components, powerconsumption may be reduced by maintaining the electronic components at alower operating temperature.

The shielding layer 170 in FIG. 1A may further include sublayers, whichare exemplarily illustrated by enlarging a portion 101 of thesemiconductor device 100 in FIG. 1B and FIG. 1C. Portions 101 b, 101 cshown in FIGS. 1B and 1C are cross-sectional views of stack-upstructures on encapsulants 160 b, 160 c covering electronic components,respectively. Of note, heights of layers of the stack-up structuresdepicted in FIG. 1B and FIG. 1C are only illustrative, not representingthe actual proportion of heights of layers in the stack-up structures.

Referring to FIG. 1B, the enlarged portion 101 b shows that a shieldinglayer 170 b may include three sublayers according to a preferredembodiment. Specifically speaking, the shielding layer 170 b may includea wetting sublayer 171 b, a shielding sublayer 172 b, and a protectionsublayer 173 b from bottom to top. That is, the wetting sublayer 171 bis formed on the encapsulant 160 b. The shielding sublayer 172 b on thewetting sublayer 171 b may be formed by sputtering, plasma deposition orspraying, so as to prevent exterior interference such as electromagneticinterference. Preferably, the shielding sublayer 172 b is formed bysputtering. The protection sublayer 173 b may be formed on the shieldingsublayer 172 b, which preferably includes stainless steel, organicsolderability preservative or nickel, so as to provide better resistancesuch as oxidation resistance, thermal shock resistance, moistureresistance, and corrosion resistance. Then a thermal interface layer 180b is disposed on the protection sublayer 173 b, and a metal lid 190 b isfurther disposed on the thermal interface layer 180 b. In someembodiments, a thickness of the wetting sublayer 171 b is less than orequal to 1 μm. In some embodiments, a thickness of the shieldingsublayer 172 b ranges from 2 μm to 10 μm, for example, 2 μm, 3 μm, 4 μm,5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm. In some embodiments, a thickness ofthe protection sublayer 173 b is less than or equal to 1 μm. However,the respective thicknesses of the above-mentioned sublayers 171 b, 172 band 173 b are not to be limited to these examples. In accordance withthe scope of the present application, the thicknesses of the sublayers171 b, 172 b and 173 b may include any thickness, which can effectivelyperform wetting, shielding and protecting, respectively.

In another embodiment, i.e., the portion 101 c shown in FIG. 1C, theshielding layer 170 c may include only two sublayers, which are awetting sublayer 171 c on the encapsulant 160 c, and a shieldingsublayer 172 c on the wetting sublayer 171 c, respectively. A thermalinterface layer 180 c is disposed on the shielding sublayer 172 c, and ametal lid 190 c is further disposed on the thermal interface layer 180c. The wetting sublayers 171 b, 171 c are generally used for providingbetter wettability for layers that are in contact with themselves.Specifically speaking, the wetting sublayer 171 b, 171 c may enable theshielding sublayers 172 b, 172 c to adhere more completely and uniformlyto the encapsulants 160 b, 160 c, respectively. The wetting sublayers171 b, 171 c are preferably made of a material including at least one ofgold, silver, indium, and tin. Preferably, the wetting sublayers 171 b,171 c includes titanium or stainless steel. The shielding sublayer isused for blocking exterior interference such as electromagneticinterference from environment or other electronic devices. Preferably,the shielding sublayers 172 b, 172 c includes copper. Aspects of thepresent application are not limited thereto, it can be appreciated thatother electronic components may be mounted on a substrate, andencapsulant and shielding may be needed on electronic components on bothsides of a substrate. Furthermore, a selective shielding and/orselective forming a thermal interface layer and/or configuring aselective metal lid can be appreciated.

FIG. 1D is a cross-sectional view illustrating a semiconductor devicewith discrete antenna packages according to an embodiment of the presentapplication. As shown in FIG. 1D, in a semiconductor device 100 d,electronic components mounted on a side of a substrate 110 d opposite toan encapsulant and aforementioned heat management layers may be discreteantenna packages 150 d. The discrete antenna packages 150 d may beformed within another encapsulant layer 151 d. The discrete antennapackages 150 d may include therein respective antenna conductivepatterns which are electrically connected to certain conductive patterns(not shown) in the substrate 110 d, so as to further connected to theother electronic components on the topside of the substrate 110 d.

In some embodiments, an encapsulant covering a plurality of electroniccomponents may be constructed to expose a top surface of at least oneelectronic component of the plurality of electronic components, thereby,a shielding layer on the encapsulant may be in contact with the topsurface of the at least one electronic component. FIG. 2A shows asemiconductor device 200 with a thinned encapsulant, according to anembodiment of the present application.

As shown in FIG. 2A, multiple electronic components including twosemiconductor dice 220, discrete devices 230, 240, and dielectricmembers 250 may be mounted on both sides of a substrate 210. It can alsobe appreciated that the dielectric members 250 may be replaced bydiscrete antenna packages configuration shown in FIG. 1D. Similar to theembodiment of FIG. 1A, the two semiconductor dice 220 and the discretedevice 230 need to be encapsulated, while other electronic componentsrequire no encapsulation. However, different from the embodiment of FIG.1A, an encapsulant 260 constructed for covering the two semiconductordice 220 and the discrete device 230 may expose top surfaces of the twosemiconductor dice 220. At the same time, some electronic componentsinside the encapsulant 260 may remain unexposed such as the discretedevice 230. A shielding layer 270 is formed on the encapsulant 260.Since the top surfaces of the semiconductor dice 220 are exposed, theshielding layer 270 is in contact with the top surfaces of the twosemiconductor dice 220. In some preferred embodiments, the shieldinglayer 270 may cover an outer surface of an encapsulant cuboid formed bythe encapsulant 260. A thermal interface layer 280 is disposed on theshielding layer 270 and conforms to a top surface of the shielding layer270. A metal lid 290 is disposed on the thermal interface layer 280 andconforms to a top surface of the thermal interface layer 280. Thematerials of the encapsulant 260, the above-mentioned layers and themetal lid 290 are similar to those described with reference to theembodiment illustrated in FIG. 1A. It can be appreciated that someelectronic components may be exposed from an encapsulant while othersmay not, which may be configured differently.

Further referring to FIG. 2A, the shielding layer 270 may furtherinclude sublayers, which are exemplarily illustrated by enlarging aportion 201 of the semiconductor device 200 in FIG. 2B and FIG. 2C.Portions 201 b, 201 c shown in FIGS. 2B and 2C are cross-sectional viewsof stack-up structures on an encapsulant covering electronic components,respectively. Particularly, a portion where a right semiconductor die220 in FIG. 2A is in contact with the shielding layer 270 is enlarged.

Referring to FIG. 2B, the enlarged portion 201 b shows that a shieldinglayer 270 b may include three sublayers according to a preferredembodiment. Of note, the enlarged portion 210 b depicts a portion wherea top surface of a semiconductor die 220 b is exposed from theencapsulant 260 in FIG. 2A, thereby the semiconductor die 220 b is incontact with the shielding layer 270 b. Specifically speaking, in thepreferred embodiment of FIG. 2B, the shielding layer 270 b may include awetting sublayer 271 b, a shielding sublayer 272 b, and a protectionsublayer 273 b from bottom to top. Then a thermal interface layer 280 bis disposed on the protection sublayer 273 b, and a metal lid 290 b isdisposed on the thermal interface layer 280 b.

In another embodiment, i.e., the portion 201 c shown in FIG. 2C, ashielding layer 270 c may only include two sublayers, which are awetting sublayer 271 c in contact with a semiconductor die 220 c, and ashielding sublayer 272 c on the wetting sublayer 271 c, respectively. Athermal interface layer 280 c is disposed on the shielding sublayer 272c, and a metal lid 290 c is disposed on the thermal interface layer 280c. The material configurations of the above-mentioned layers and themetal lid may refer back to the illustrations of FIGS. 1B and 1C.

In some other embodiments, an electronic component mounted on asubstrate may be a semiconductor package, which may include one or moresemiconductor dice and/or one or more discrete devices. Such embodimentscan refer to FIGS. 3A, 3B and 4 , which depict the situation thatencapsulation, shielding and layers for heat management are constructedon a semiconductor package of multiple electronic components mounted ona substrate.

FIG. 3A shows a semiconductor device 300 according to an embodiment ofthe present application. Referring to FIG. 3A, in the semiconductordevice 300, multiple electronic components may be mounted on a substrate310. That is, a semiconductor package 320, discrete devices 340, anddielectric members 350 may be mounted on the substrate 310 andelectrically connected together via conductive structures in thesubstrate 310. It can also be appreciated that the dielectric members350 may be replaced by a discrete antenna packages configuration asshown in FIG. 1D. The semiconductor package 320 may include multiplecomponents such as a substrate 321, two semiconductor dice 322 anddiscrete devices 323 mounted on one side of the substrate 321, and onesemiconductor die 324 on the other side of the substrate 321. Electroniccomponents mounted on the substrate 321 are electrically connectedtogether via the conductive structures in the substrate 321. Of note,part of the semiconductor package 320 may be previously encapsulated insome embodiments. The substrate 321 of the semiconductor package 320 maybe electrically connected to the substrate 310 via such as solder balls325. In this embodiment, the semiconductor package 320 is encapsulatedwith an encapsulant 360, forming an encapsulant cuboid similar to theembodiment of FIG. 1A. In some embodiments, the semiconductor die 324disposed between the substrate 321 and the substrate 310 may expose asurface facing the substrate 310 from the encapsulant 360 as illustratedin FIG. 3A. A shielding layer 370 is formed on the encapsulant 360 tocover at least part of the outer surface of the encapsulant 360.Preferably, the shielding layer 370 covers all the outer surface of theencapsulant cuboid. The shielding layer 370 includes a top sectioncovering a top surface of the encapsulant cuboid, and a lateral sectioncovering lateral surfaces of the encapsulant cuboid. A thermal interfacelayer 380 is further formed on the shielding layer 370. Preferably, thethermal interface layer 380 may fully cover the top section of theshielding layer 370, and may not cover the lateral section of theshielding layer 370. That is, the thermal interface layer 380 conformsto the top section of the shielding layer. A metal lid 390 is furtherdisposed on the thermal interface layer 380. Preferably, the metal lid390 may fully cover a top surface of the thermal interface layer 380.That is, the metal lid 390 conforms to the top surface of the thermalinterface layer 380. It can be appreciated that the shielding layer 370of the semiconductor device 300 may be the shielding layer 101 b or 101c, which includes three or two sublayers, respectively.

Referring to FIG. 3B, a semiconductor device 300 b may be configuredsimilarly to FIG. 3A. That is, a semiconductor package 320 may bemounted via solder balls 325 to a substrate 310 of the semiconductordevice 300 b. In this embodiment, the semiconductor package 320 alsoincludes a substrate 321, two semiconductor dice, and discrete devices323 a, 323 b. Different from FIG. 3A, the discrete device 323 b of thesemiconductor package 320 requires no encapsulation, therefore, anencapsulant 360 is not formed on the discrete device 323 b. That is tosay, the encapsulant 360 is formed on part of the semiconductor package320.

FIG. 4 shows a semiconductor device 400 according to an embodiment ofthe present application. Referring to FIG. 4 , the semiconductor device400 with mounted semiconductor package 420 is shown. Similar to FIG. 2A,the semiconductor package 420 is mounted on a substrate and requiresthermal interface layer and metal lid, and an encapsulant 460 may alsobe constructed to expose a top surface of at least one electroniccomponent of the semiconductor package 420. It can be appreciated thatsuch configuration may be adapted for a semiconductor packageconfiguration as shown in FIG. 3B. In a preferred embodiment, topsurfaces of two semiconductor dice 422 are exposed from the encapsulant460. In this case, a shielding layer 470 formed on the encapsulant 460is in contact with the top surfaces of the two semiconductor dice 422.Yet other electronic components inside the encapsulant 460 may remainunexposed and not in contact with the shielding layer 470. A thermalinterface layer 480 is disposed on the shielding layer 470. A metal lid490 is disposed on the thermal interface layer 480.

The above embodiments show that the thermal interface layer and themetal lid are disposed on top of the shielding layer. In yet anotheraspect, a thermal interface layer and a metal lid may be configuredunderneath a shielding layer, as illustrated in the embodiments shown inFIGS. 5A-8 .

FIG. 5A shows a semiconductor device 500 according to an embodiment ofthe present application. As shown in FIG. 5A, a thermal interface layer580 is disposed on a top surface of an encapsulant cuboid formed by anencapsulant 560 and electronic components covered by the encapsulant560. The thermal interface layer 580 conforms to a top surface of theencapsulant cuboid. A metal lid 590 is disposed on the thermal interface580, which conforms to a top surface of the thermal interface 580. In apreferred embodiment, a shielding layer 570 is disposed on the metal lid590 to cover a top surface of the metal lid 590, lateral surfaces of theencapsulant cuboid, lateral surfaces of the thermal interface layer 580and lateral surfaces of the metal lid 590.

The shielding layer 570 in the semiconductor device 500 shown in FIG. 5Amay further include sublayers according to two other embodiments, whichare illustrated by enlarging a portion 501 of the semiconductor device500 in FIG. 5B and FIG. 5C. Portions 501 b, 501 c are cross-sectionalviews of stack-up structures on encapsulants 560 b, 560 c coveringelectronic components.

General laminate structures shown in FIG. 5B and FIG. 5C are both theencapsulants 560 b, 560 c, thermal interface layers 580 b, 580 c, metallids 590 b, 590 c and shielding layers 570 b, 570 c from bottom to top,respectively. The difference of the two general laminate structuresshown in FIG. 5B and FIG. 5C lies in sublayers of the shielding layers570 b, 570 c. Referring to FIG. 5B, an enlarged portion 501 b shows thatthe shielding layer 570 b may include three sublayers according to apreferred embodiment. Specifically speaking, the shielding layer 570 bmay include a wetting sublayer 571 b, a shielding sublayer 572 b, and aprotection sublayer 573 b from bottom to top. In another embodiment 501c shown in FIG. 5C, the shielding layer 570 c may only include twosublayers, which are a shielding sublayer 572 c on the metal lid 590 c,and a protection sublayer 573 c on the shielding sublayer 572 c.

FIG. 6 shows a semiconductor device 600 according to an embodiment ofthe present application. Similar to the embodiment shown in FIG. 5A, athermal interface layer 680 and a metal lid 690 are also beneath ashielding layer 670, yet here an encapsulant 660 is configured to exposea top surface of at least one electronic component inside theencapsulant 660, which is similar to the embodiment shown in FIG. 2A. InFIG. 6A, the encapsulant 660 covering a plurality of electroniccomponents may be constructed to expose top surfaces of twosemiconductor dice 620, thereby the thermal interface layer 680 is incontact with the two semiconductor dice 620. The metal lid 690 isdisposed on the thermal interface layer 680, both of which have a samearea as a top surface of an encapsulant cuboid formed by the encapsulant660. The shielding layer 670 is formed on the metal lid 690. It can beappreciated that similar to FIG. 5A, the shielding layer 670 may cover atop surface of the metal lid 690, lateral surfaces of the metal lid 690,lateral surfaces of the thermal interface layer 680, and the lateralsurfaces of the encapsulant cuboid.

Similar to the semiconductor device 500 shown in FIG. 5A, the shieldinglayer 670 in the semiconductor device 600 may further include sublayersaccording to two other embodiments, which are illustrated by enlarging aportion 601 of the semiconductor device 600 in FIG. 6B and FIG. 6C.Portions 601 b, 601 c are cross-sectional views of stack-up structureson an encapsulant 660 covering electronic components. Particularly, aportion where a right semiconductor die 620 in FIG. 6A is in contactwith the shielding layer 670, is enlarged.

General laminate structures of the embodiments shown in FIG. 6B and FIG.6C are both semiconductor dice 620 b, 620 c, thermal interface layers680 b, 680 c, metal lids 690 b, 690 c, and shielding layers 670 b, 670 cfrom bottom to top, respectively. The difference of the two generallaminate structures shown in FIG. 6B and FIG. 6C lies in sublayers ofthe shielding layers 670 b, 670 c. Referring to FIG. 6B, the enlargedportion 601 b shows that the shielding layer 670 b may include threesublayers, i.e., a wetting sublayer 671 b, a shielding sublayer 672 b,and a protection sublayer 673 b from bottom to top. The three sublayersof the shielding layer 670 b are formed on the metal lid 690 b. Inanother embodiment 601 c shown in FIG. 6C, the shielding layer 670 c mayonly include two sublayers, which are a shielding sublayer 672 c and aprotection sublayer 673 c on the shielding sublayer 672 c, respectively.

Similar to the embodiments shown in FIGS. 3 and 4 , an electroniccomponent mounted on a substrate may be a semiconductor package, whichmay include one or more semiconductor dice and/or one or more discretedevices. In this situation, a thermal interface layer and a metal lidmay also be configured beneath a shielding layer, which can refer toFIGS. 7 and 8 .

FIG. 7 shows a semiconductor device 700 according to an embodiment ofthe present application. Referring to FIG. 7 , in the semiconductordevice 700, multiple electronic components are mounted on a substrate710. That is, a semiconductor package 720, discrete devices 740,dielectric members 750 are mounted on the substrate 710 and electricallyconnected with each other via the substrate 710. It can also beappreciated that the dielectric members 750 may be replaced by adiscrete antenna packages configuration as shown in FIG. 1D. Thesemiconductor package 720 may include multiple components as shown inFIG. 7 . In this embodiment, the semiconductor package 720 isencapsulated with an encapsulant 760, forming an encapsulant cuboid. Onthe periphery of the encapsulant 760, there are a thermal interfacelayer 780 and a metal lid 790, both of which have a same area as a topsurface of the encapsulant cuboid. A shielding layer 770 further coversa top surface of the metal lid 790, lateral surfaces of the metal lid790, lateral surfaces of the thermal interface layer 780, and lateralsurfaces of the encapsulant cuboid. It can be appreciated that theshielding layer 770 may be the same as or similar to the shielding layer501 b or 501 c shown in FIGS. 5B and 5C. It can be appreciated that suchconfiguration may be adapted for a semiconductor package configurationas shown in FIG. 3B.

FIG. 8 shows a semiconductor device 800 according to an embodiment ofthe present application. Referring to FIG. 8 , an encapsulant 860exposing a top surface of at least one electronic component in asemiconductor package 820 mounted on a substrate is shown. Similar tothe semiconductor device 600 shown in FIG. 6A, a thermal interface layer880 is in contact with top surfaces of two semiconductor dice 822, whichare exposed from the encapsulant 860. Other electronic components of thesemiconductor package 820 remain covered by the encapsulant 860. A metallid 890 is disposed on the thermal interface layer 880, both of whichhave a same area as a top surface of an encapsulant cuboid formed by theencapsulant 860. A shielding layer 870 further covers a top surface ofthe metal lid 890, lateral surfaces of the metal lid 890, lateralsurfaces of the thermal interface layer 880, and the lateral surfaces ofthe encapsulant cuboid. It can be appreciated that the shielding layer870 of the semiconductor device 800 may be the same as or similar to theshielding layer 601 b or 601 c shown in FIGS. 6B and 6C. It can beappreciated that such configuration may be adapted for a semiconductorpackage configuration as shown in FIG. 3B.

In FIGS. 9A-10F, steps for making an aforementioned semiconductor deviceare illustrated. Note that the sequential order illustrated belowrepresents only some of the embodiments and could be adapted to specificscenarios.

FIG. 9A is a flowchart illustrating a method 900 for making asemiconductor device according to an embodiment of the presentapplication. Herein, a substrate is firstly provided in block 901, thenat least one electronic component is mounted thereon in block 902. Afterthat, an encapsulant is formed on the substrate in block 903, at leastpartially encapsulating the at least one electronic component. Ashielding layer is formed in block 904, a thermal interface layer isformed in block 905 and a metal lid is formed in block 906. Of note, asillustrated in the above embodiments, the forming of the shielding layermay be before the forming of the thermal interface layer in block 904and the forming of the metal lid in block 905, or after these twoblocks. Of note, for a case that a semiconductor package includingmultiple electronic components is mounted on a substrate, part or all ofthe semiconductor package may be previously encapsulated.

FIGS. 9B to 9E illustrates various steps for making a semiconductordevice according to the method shown in FIG. 9A on the providedsubstrate 910. As shown in FIG. 9B, a substrate 910 is provided, where aplurality of electronic components, such as two semiconductor dice 920,discrete devices 930, 940 and dielectric members 950 are firstly mountedby for example solder paste printing and reflowing. Then in FIG. 9C, anencapsulant 960 is formed, which encapsulates some of theabove-mentioned electronic components such as the two semiconductor dice920 and the discrete device 930 by molding. Next, in FIG. 9D, ashielding layer 970, preferably fully covering the encapsulant 960 andthe encapsulated electronic components, is deposited by for examplesputtering. Then in FIG. 9E, a thermal interface layer 980 is disposedon the shielding layer 970 by dispensing. Next in FIG. 9F, a metal lid990 is attached on the thermal interface layer 980.

In method 1000, forming of a shielding layer 1004 may be after formingof a thermal interface layer 1005 and forming of a metal lid 1006 asmentioned before. Of note, for a case that a semiconductor packageincluding multiple electronic components is mounted on a substrate, partof the semiconductor package may be previously encapsulated.

FIGS. 10B to 10F illustrates various steps for making a semiconductordevice according to the method shown in FIG. 10A. As shown in FIG. 10B,a substrate 1010 is provided, where a plurality of electroniccomponents, such as two semiconductor dice 1020, discrete devices 1030,1040 and dielectric members 1050 are firstly mounted by for examplesolder paste printing and reflowing. Then in FIG. 10C, an encapsulant1060 is formed, which encapsulates some of the above-mentionedelectronic components such as the two semiconductor dice 1020 and thediscrete device 1030 by molding. The two aforementioned steps aresimilar to the case in the method 900. Next, in FIG. 10D, a thermalinterface layer 1080, preferably covering a top surface of theencapsulant 1060 and the encapsulated electronic components, is disposedby for example dispensing. Next in FIG. 10E, a metal lid 1090 isattached on the thermal interface layer 1080. Finally, a shielding layer1070 in FIG. preferably fully covering the thermal interface layer 1080,the metal lid 1090, the encapsulant 1060 and the encapsulated electroniccomponents, is deposited by for example sputtering.

It can be appreciated that the aforementioned steps in FIGS. 9B-9F,FIGS. 10B-10F may be adapted for any one of the aforementionedsemiconductor device in FIGS. 1A-8 .

It can be seen from the above embodiments that the present applicationinvolves a stack-up structure of shielding, thermal interface layer andmetal lid. This structure introduces heat management to a semiconductordevice without affecting the general structure of a normal semiconductordevice. Therefore, the present application provides a semiconductordevice with heat management and is widely applicable.

The discussion herein included numerous illustrative figures that showedvarious portions of a semiconductor device and method of manufacturingthereof. For illustrative clarity, such figures did not show all aspectsof each example assembly. Any of the example assemblies and/or methodsprovided herein may share any or all characteristics with any or allother assemblies and/or methods provided herein.

Various embodiments have been described herein with reference to theaccompanying drawings. It will, however, be evident that variousmodifications and changes may be made thereto, and additionalembodiments may be implemented, without departing from the broader scopeof the invention as set forth in the claims that follow. Further, otherembodiments will be apparent to those skilled in the art fromconsideration of the specification and practice of one or moreembodiments of the invention disclosed herein. It is intended,therefore, that this application and the examples herein be consideredas exemplary only, with a true scope and spirit of the invention beingindicated by the following listing of exemplary claims.

1. A semiconductor device, comprising: a substrate; at least oneelectronic component mounted on the substrate; an encapsulant formed onthe substrate and at least partially encapsulating the at least oneelectronic component; a shielding layer formed on the encapsulant; athermal interface layer formed on the shielding layer; and a metal lidformed on the thermal interface layer.
 2. The semiconductor device ofclaim 1, wherein the shielding layer comprises: a wetting sublayer; anda shielding sublayer formed on the wetting sublayer.
 3. Thesemiconductor device of claim 2, wherein the shielding layer furthercomprises a protection sublayer formed on the shielding sublayer.
 4. Thesemiconductor device of claim 3, wherein the protection sublayercomprises stainless steel, organic solderability preservative, ornickel.
 5. The semiconductor device of claim 2, wherein the wettingsublayer comprises stainless steel or titanium; and the shieldingsublayer comprises copper.
 6. The semiconductor device of claim 1,wherein the encapsulant is constructed that a top surface of the atleast one electronic component is exposed from the encapsulant to be incontact with the shielding layer.
 7. The semiconductor device of claim1, wherein the thermal interface layer comprises a solder paste.
 8. Asemiconductor device, comprising: a substrate; at least one electroniccomponent mounted on the substrate; an encapsulant formed on thesubstrate and at least partially encapsulating the at least oneelectronic component; a thermal interface layer formed on theencapsulant; a metal lid formed on the thermal interface layer; and ashielding layer formed on the substrate and covering the metal lid, thethermal interface layer and the encapsulant.
 9. The semiconductor deviceof claim 8, wherein the shielding layer comprises: a shielding sublayer;and a protection sublayer formed on the wetting sublayer.
 10. Thesemiconductor device of claim 9, wherein the shielding layer furthercomprises a wetting sublayer formed underneath the shielding sublayer.11. The semiconductor device of claim 10, wherein the wetting sublayercomprises stainless steel or titanium.
 12. The semiconductor device ofclaim 9, wherein the shielding sublayer comprises copper; and theprotection sublayer comprises stainless steel, organic solderabilitypreservative, or nickel.
 13. The semiconductor device of claim 8,wherein the encapsulant is constructed that a top surface of the atleast one electronic component is exposed from the encapsulant to be incontact with the shielding layer.
 14. The semiconductor device of claim8, wherein the thermal interface layer includes a solder paste.
 15. Amethod for making a semiconductor device, comprising: providing asubstrate; mounting at least one electronic component on the substrate;forming an encapsulant on the substrate and at least partiallyencapsulating the at least one electronic component; forming a shieldinglayer on the encapsulant; forming a thermal interface layer on theshielding layer; and forming a metal lid on the thermal interface layer.16. The method of claim 15, wherein the shielding layer comprises: awetting sublayer; and a shielding sublayer formed on the wettingsublayer.
 17. The method of claim 16, wherein the shielding layerfurther comprises a protection sublayer formed on the shieldingsublayer.
 18. The method of claim 15, wherein the encapsulant isconstructed that a top surface of the at least one electronic componentis exposed from the encapsulant to be in contact with the shieldinglayer.
 19. The method of claim 15, wherein the encapsulant isconstructed to cover a top surface and lateral surfaces of the at leastone electronic component.
 20. A method for making a semiconductordevice, comprising: providing a substrate; mounting at least oneelectronic component on the substrate; forming an encapsulant on thesubstrate and at least partially encapsulating the at least oneelectronic component; forming a thermal interface layer on theencapsulant; forming a metal lid on the thermal interface layer; andforming a shielding layer on the substrate and covering the metal lid,the thermal interface layer and the encapsulant.